module specialMemoryManager (
    input wire clk,
    input wire rst,
    input wire ram_pick,
    input wire write_en,
    input wire [9:0] write_size,
    input wire [5:0] write_priority,
    input wire [15:0] write_port,
    input wire data_en_in,
    input wire [31:0] data_in,
    input wire dequeue_en,
    input wire [9:0] dequeue_value,
    input wire [15:0] enqueue_sucess,
    input wire enqueue_ack,
    output wire enqueue_en_out,
    output wire [5:0] enqueue_priority_out,
    output wire [9:0] enqueue_value_out,
    output wire [15:0] enqueue_port_out,
    output wire dequeue_success,
    output wire address_ready,
    output wire manager_read_ready,
    output wire manager_write_ready,
    output reg data_en_out,
    output reg [31:0] data_out
);
    //RAM驱动信号
    wire write_padding_out;                 
    wire write_en_ram;  
    wire [12:0] write_address_out;
    wire [31:0] write_data_out;
    wire read_en_out;
    wire [12:0] read_address_out;
    //RAM控制信号
    wire ena;
    wire wea;
    wire [12:0] addra;
    wire [31:0] dina;
    wire enb;
    wire web;
    wire [12:0] addrb;
    wire [31:0] dinb;
    wire [31:0] data_out_a, data_out_b;
    reg [1:0] work_state;
    reg [3:0] delay;

    //数据输出
    always @(posedge clk) begin
        if (rst) begin
            work_state <= 2'b00;
        end
        else begin
            if (work_state==2'b00 && read_en_out) begin
                work_state <= 2'b01;
            end

            if (work_state==2'b01 && data_out_b>0) begin
                data_out <= data_out_b;
                data_en_out <= 1;
                work_state <= 2'b10;
            end

            if (work_state==2'b10) begin
                data_out <= data_out_b;
                data_en_out <= 1;
                if (read_en_out==0) begin
                    delay <= 3;
                    work_state <= 2'b11;
                end
            end

            if (work_state==2'b11) begin
                if (delay == 0) begin
                    data_out <= 0;
                    data_en_out <= 0;
                    work_state <= 2'b00;
                end
                else begin
                    data_out <= data_out_b;
                    data_en_out <= 1;
                    delay <= delay - 1;
                end
            end
        end
    end


    //空间分配
    specialMemoryAlloctor alloctor (.clk(clk), .rst(rst), 
                                .ram_pick(ram_pick), .write_en(write_en), .write_size(write_size), .write_priority(write_priority), .write_port(write_port), 
                                .data_en_in(data_en_in), .data_in(data_in), 
                                .dequeue_en(dequeue_en), .dequeue_value(dequeue_value), .enqueue_sucess(enqueue_sucess), .enqueue_ack(enqueue_ack),
                                .enqueue_en(enqueue_en_out), .enqueue_port(enqueue_port_out), .enqueue_priority(enqueue_priority_out), .enqueue_value(enqueue_value_out), .dequeue_success(dequeue_success), 
                                .address_ready(address_ready), .manager_write_ready(manager_write_ready), .manager_read_ready(manager_read_ready),
                                .write_padding_out(write_padding_out), .write_en_out(write_en_ram), .write_address_out(write_address_out), .write_data_out(write_data_out), 
                                .read_en_out(read_en_out), .read_address_out(read_address_out));
    
    
    //RAM读写驱动�??
    memoryWorker worker(.clk(clk), .rst(rst), .wr_padding_en(write_padding_out), .wr_en(write_en_ram), .wr_address(write_address_out), .wr_data(write_data_out), .rd_en(read_en_out), .rd_address(read_address_out), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .enb(enb), .web(web), .addrb(addrb), .dinb(dinb));

    //RAM
    RAM_IP ram(.clka(clk), .ena(ena), .wea(wea), .addra(addra), .dina(dina), .douta(data_out_a), .clkb(clk), .enb(enb), .web(web), .addrb(addrb), .dinb(dinb), .doutb(data_out_b));
endmodule